Physical Design Engineer
- Work for physical design and development activities of compay's Ghz ARM-based microprocessors
- Involve in activities encompass physical design and analysis of complex and timing-critical microprocessor partition blocks and TOP
- Technical disciplines include synthesis, floor-planning, place and route, RC extraction, timing and power optimization
- Mainly cadence Based Tools [ Encounter – EDI / Innovus ]
- Involve in activities encompass Static Timing Analysis on advanced process nodes (28nm, 20nm, 16nm & beyond)
- Technical disciplines include STA, and analysis of complex and timing-critical microprocessor
- Work closely with RTL function designers and physical designers to optimize design components such as timing and power
- Fully responsible for Netlist-to-GDS physical design implementation of low power chips
- Responsible for physical design, development for variety of SoC(System On Chip) and tapeout.
- Execute state-of-art methodologies include, floor-planning, place and route, RC extraction, timing and power optimization, physical verification.
- Doing benchmarking on Performance/Power/Area to validate the robustness of APR flow.
- Enhance project efficiency by using Perl, TCL, Python etc.
- Minimum 5 years of high-speed CPU/GPU/DSP Subsystem RTL Integration experience or IP/Block/SoC Design experience. (Candidate with less than 5 years of relevant experience will be considered for junior position)
- Experience in ARM/IMG/Tensilica Processor Familiarity, Silicon Debug and/or Functional/Direct Test Verification
- Familiar with assertion based verification (SVA) & System Verilog language
- Experience in Processor verification, FPGA verification and/or Formal verification
- Experience with Synopsys ICC (preferred) or Cadence or Magma tools from netlists to GDS is a must
- Experience in graphics processor implementation/power reduction flows and methodology from RTL to GDS (including synthesis, floor-planning, placement, CTS, routing, timing optimization, physical verification) is a plus
- Knowledge of high-speed/low power IP and custom circuit design is a plus
- Experience with power noise and reliability tools such as Redhawk and Voltus
- Good communication and scripting skills
- Experience in physical design with tape-outs
- Knowledge of complete Netlist-to-GDS flow, Synopsys/Cadence tools like ICC or Encounter
- Good in script programming with Perl, TCL/TK or other languages
- Bachelor/Masters Degree in Electrical/Computer Engineering.
If you are ready to join this exciting opportunity, please click on the APPLY BUTTON. Alternatively, you can contact our consultant Pham Trang at +84 33 662 5134 or via email to firstname.lastname@example.org for immediate consideration.
- Thuy Trang Pham