Added 40 days ago

SoC Verification Design Engineer

LocationSingapore

Job typePermanent

Salary82,500,000-132,000,000 (VND)

CategoryEngineering

Experience7-10 Years

IndustryElectronics


Job Responsibilities

·        Undertake a technical leadership position in Digital and Analog-Mixed Signal Verification at SOC.

·         Execute SoC verification tasks and work closely with team members to review and understand the relevant functional and safety-related requirements.

· Write verification plans to meet these requirements after close alignment with other verification teams for proper work split according to mutually acceptable verification assignment.

·   Execute the verification plan by developing C/C++ testcases and System Verilog/UVM test-bench components and by integrating 3rd part VIP components.

·   Leading a team technically through exploring new environments and identifying potential enhancement areas through new methodology.

·        Identify and setting mid/long term goals based on benchmarking against industry standards.


Experience requirements

·        Undertake a technical leadership position in Digital and Analog-Mixed Signal Verification at SOC.

·        Execute SoC verification tasks and work closely with team members to review and understand the relevant functional and safety-related requirements.

·        Write verification plans to meet these requirements after close alignment with other verification teams for proper work split according to mutually acceptable verification assignment.

·        Execute the verification plan by developing C/C++ testcases and System Verilog/UVM testbench components and by integrating 3rd part VIP components.

·        Leading a team technically through exploring new environments and identifying potential enhancement areas through new methodology.

·        Identify and setting mid/long term goals based on benchmarking against industry standards.


Contact Person

  •   Phuong Nguyen
  •  Adecco