Senior Engineer - Digital Functional Verification

Job summary

Our Client - a reputable IC corporation is looking for candidates for Senior Engineer - Digital Functional Verification role

Job Responsibilities

• Be responsible for verification quality of IP and SoC modules
• Execute verification tasks and test suites based on design specification
• Analyze simulation and regression results
• Support and work closely with Digital Verification leads on self-checking test benches using modern verification techniques based on System Verilog and UVM methodology
• Support Digital Verification leads in defining new trends of verification methodologies and flows

Experience requirements

• At least 3-5 years of work experience in digital verification within the semiconductor industry
• Proven knowledge of System Verilog and UVM, VHDL or Verilog – Formal verification would be plus
• Have good programming skills, e.g., in C++, Python or Perl, as well as good Linux skills
• Good communication in English language

Education requirements

• A degree in Electrical Engineering, Information Technology or comparable with focus on electronics 

Please click the APPLY button or contact Ms. Phuong Nguyen at +84 975 625 919 or thuphuong.nguyen@adecco.com to discuss further.

Contact Person

•   Phuong Nguyen
•  Adecco