DFT Technical Lead

Job summary

Adecco's client - a famous IC design company

Job Responsibilities

As the DFT Technical Lead, you will report to Project Manager and Head of Design and be responsible for the following:

• Design, implement and verify hardware Design-for-Test, (DFT) features, including Boundary Scan, Internal SCAN with compression, ATPG (Stuck-at/Atspeed), MBIST, and JTAG/IJTAG circuitry
• Responsible for development of innovative DFT IP in collaboration with the cross-functional teams, and play a key role in full chip design integration with the testability features integrated in RTL or gate level netlist
• Work independently to generate test plans, run simulations and debug failures on DFT circuit
• Work closely with the RTL design/Design verification and Physical design teams to enable the integration and validation of test logic in all phases of the design
•  Work in close collaboration with test engineering team to deliver ATE patterns and support post silicon bring-up debugging

Experience requirements

• At least seven years of DFT engineering experience
•  Experience in leading a team (>2 member) and training new member in the overall process
• Ability to work on two or more projects simultaneously
• Strong support for team members
• Good at English is a plus

Education requirements

If you are ready to join this job opportunity, please click on APPLY BUTTON or reach out to Mr. Hai Nguyen via hai.nguyen@adecco.com for immediate attention. 

Contact Person

•   Hai Nguyen
•  Adecco