Job summary

Job Responsibilities

As the DFT Tech Lead, you will report to Manager and be responsible for the following:

• Design, implement and verify hardware Design-for-Test, (DFT) features, including Boundary Scan, Internal SCAN with compression, ATPG (Stuck-at/Atspeed), MBIST, and JTAG/IJTAG circuitry
• Responsible for development of innovative DFT IP in collaboration with the cross-functional teams, and play a key role in full chip design integration with the testability features integrated in RTL or gate level netlist
• Work independently to generate test plans, run simulations and debug failures on DFT circuit
• Work closely with the RTL design/Design verification and Physical design teams to enable the integration and validation of test logic in all phases of the design
•  Work in close collaboration with test engineering team to deliver ATE patterns and support post silicon bring-up debugging

Experience requirements

• At least 7 years of DFT engineering experience.
• Experience in leading a team (>2 member) and training new member in the overall process
• Ability to work on two or more projects simultaneously
• Strong support for team members
• Good at English is a plus.

Education requirements

Please click the APPLY button or contact Ms. Thu Trang (Tracy) Nguyen via +84 985 236 870 or trang.nguyen@adecco.com to discuss further.

Contact Person

• Trang Nguyen
• Adecco
• Tel.