Design Verification Engineer

Job summary

·        As the Design Verification Engineer (Logic Verification Engineer), you will build and verify a part of ASIC, include making verification environment, create verification plan, module verification, top verification, integration verification, functional and code coverage for a US communication company. Support our ODM and OEM manufacturing partners.

·        Partner with system engineers, hardware engineers, and embedded software engineers to refine existing product verification, to develop new cutting-edge implementations in support of vendor, customer and standard requirements.

Job Responsibilities

• Build and verify a part of ASIC, include making verification environment, create verification plan, module verification, top verification, integration verification, functional and code coverage for a US communication company.
• Support our ODM and OEM manufacturing partners.
• Partner with system engineers, hardware engineers, and embedded software engineers to refine existing product verification, to develop new cutting-edge implementations in support of vendor, customer and standard requirements.

Experience requirements

• Expert with working experience of ASIC/SoC/FPGA product development
• Deep understanding of UVM verification, Verilog and System Verilog for synthesis and verification
• Familiar with digital simulation tools and debugging techniques
• Have experience of reading and understanding global industry standards and requirements for communication devices Have experience of documentation, writing technical reports and composing technical documents

Education requirements

• Bachelor of engineer, major in Telecommunication, Electronics is a plus

If you are ready to join this exciting opportunity, please contact Ms. Pham Trang at +84 33 662 5134 (Call/iMess/Whatsapp/Zalo/Viber) or via email to trang.pham@adecco.com for immediate consideration.

Contact Person

•   Thuy Trang Pham
•  Adecco