Design Verification Engineer

Job summary

Adecco's client, a highly reputable international semiconductor manufacturer founded in 1999. The company has almost 50 thousand employees and is one of the ten largest semiconductor manufacturers worldwide. It is market leader in automotive and power semiconductors.

Job Responsibilities

• Create and define verification plans;
• Develop verification environments for our ICs using Universal Verification Methodology (UVM);
• Draw on test scenarios using SystemVerilog;
• Verify functionality using the Constrained Random approach;
• Develop assertions in SystemVerilog for formal verification;
• Interact with other disciplines, such as Concept and Application Engineering, to define verification plans and strategies;
• Provide proactive support to users of our verification flow environment;
• Be responsible for our verification methods;

Experience requirements

• Have at least 2 years of experience in Metric Driven Verification (digital and/or mixed-signal);
• Have capabilities and expertise in working with microcontroller-based ICs, as well as security and safety requirements;
• Have excellent know-how with UVM especially using SystemVerilog;
• Have knowledge of Design Verification or RTL design (VHDL);
• Ideally have knowledge of Cadence verification software;

Education requirements

• A Bachelor’s degree in Electrical Engineering, Computer Science, or a similar academic discipline

The role offers competitive remuneration package with supportive working environment. If you are ready to explore more about this exciting opportunity, please contact our Recruitment Manager Ms. Van Anh Nguyen at +84 83 246 6688 (Call/iMess/Whatsapp/Zalo/Viber) or via email to vananh.nguyen@adecco.com for a confidential discussion.

Contact Person

•   Van Anh Nguyen
•  Adecco