Job summary

Job Responsibilities

As the Senior / Staff Engineer, you will be responsible for the following: 

• Be responsible for verification quality of IP and SoC modules
• Execute verification tasks and test suites based on design specifications
• Analyze simulation and regression results
• Support and work closely with Digital Verification leads onself-checking test benches using modern verification techniques based on System Verilog and UVM methodology
• Support Digital Verification leads in defining new trends of verification methodologies and flows

Experience requirements

• At least 2 years of work experience in digital verification within the semiconductor industry
• Candidates with more years of relevant experience will be considered for a more senior role.

Education requirements

• University degree in Electrical Engineering, Information Technology or comparable with focus on electronics

Click the APPLY button or don't hesitate to contact Ms. Van Anh (Sophia) at vananh.nguyen@adecco.com or +84 83 246 6688 for further discussion. Thank you!

Contact Person

• Van Anh Nguyen
• Adecco
• Tel.